The present invention relates to a current mirror circuit used for a semiconductor integrated circuit and the like, and particularly to a cascode current mirror circuit that operates at a low voltage.
Generally, current mirror circuits are used as current amplifiers and the like for supplying output currents proportional to input currents. Further, in a case where it is required to supply an output current with high precision, a plurality of current mirror circuits are concatenated into a so-called cascode constitution to obtain a large output resistance.
FIG. 1 is a circuit diagram showing an exemplary structure of a general cascode current mirror circuit.
In FIG. 1, the current mirror circuit such as in a two-staged cascode constitution comprises four n-channel MOS transistors 11 to 14, a current source 3, and an output terminal 4. In this circuit structure, a first stage current mirror circuit and a second stage current mirror circuit are made up by the n-channel MOS transistors 11, 12 and the n-channel MOS transistors 13, 14, respectively, and the first stage current mirror circuit and the second stage current mirror circuit are mutually concatenated.
The current mirror circuit having such a constitution is input with an input current lin through a drain terminal of the n-channel MOS transistor 11, to output an output current lo through a drain terminal of the n-channel MOS transistor 12.
Assuming now that each of the n-channel MOS transistors 11 to 14 has a threshold voltage Vth and a value obtained by subtracting the threshold voltage Vth from a gate/source voltage Vgs of each of the n-channel MOS transistors 11 to 14 is xcex1 (i.e., Vgs-Vth=xcex1; assuming that a drain current is equal to the input current lin), a gate voltage value of the n-channel MOS transistor 14 becomes Vth+xcex1 and a gate voltage value of the n-channel MOS transistor 12 becomes 2(Vth+xcex1).
FIG. 2 is a graph showing a relationship between an output voltage Vo and the output current lo in the current mirror circuit of FIG. 1.
In FIG. 2, when a value of the output voltage Vo (a voltage of the output terminal 4 connected to the drain terminal of the n-channel MOS transistor 12) is 2xcex1 or less, each of the n-channel MOS transistors 12, 14 operates in a non-saturation region (triode region); and when the value of the output voltage Vo is between 2xcex1 and (Vth+2xcex1), the n-channel MOS transistor 12 operates in the non-saturation region and the n-channel MOS transistor 14 operates in a saturation region (pinch-off region). Further, when the value of the output voltage Vo is Vth+2xcex1 or higher, each of the n-channel MOS transistors 12, 14 operates in the saturation region. Namely, in the region where the value of the output voltage Vo is Vth+2xcex1 or higher, an inclination of curve Vo-lo is extremely small to thereby attain an extremely large output resistance, so that the output current lo with high precision can be obtained.
However, to obtain the output current lo with high precision, the cascode current mirror circuit as described above is required to operate at an input voltage of 2(Vth+xcex1) or higher and at the output voltage Vo of Vth+2xcex1 or higher, causing a problem of narrow settable ranges for the input/output voltages, and resulting in difficulty particularly in using the current mirror circuit in a low voltage circuit.
For example, as shown in FIG. 3, in a case where an output terminal of a p-channel cascode current mirror circuit is connected to an input terminal of an n-channel cascode current mirror circuit to thereby fold an electric current, since a voltage of 2(Vthn+xcex1n)+(Vthp+2xcex1p) or higher is required as a supply voltage Vc (in which subscripts n and p of respective parameters represent corresponding channels, respectively), for example, when Vthn=Vthp=1V and xcex1n=xcex1p=0.1V, these cascode current mirror circuits are unable to be used at a general supply voltage of 3.3V.
In view of the above, there has been proposed a circuit structure for lowering an input voltage and an output voltage, for example, a compound current mirror circuit known from U.S. Pat. No. 4,477,782 and the like.
Such as shown in FIG. 4, this compound current mirror circuit has a circuit structure in which an n-channel MOS transistor 11xe2x80x2 and a current source 3xe2x80x2 are, added to the current mirror circuit shown in FIG. 1, such that a ratio (W/L) of gate width to gate length in the n-channel MOS transistor 11xe2x80x2 is xc2xc times the W/L of each of other n-channel MOS transistors 11 to 14.
In such a compound current mirror circuit, the gate voltage of the n-channel MOS transistor 12 becomes Vth+2xcex1. Thus, each of the n-channel MOS transistors 12, 14 operates in the saturation region when the value of the output voltage Vo is 2xcex1 or higher, as shown in FIG. 5. Further, the voltage at the input terminal (i.e., the drain voltage of the n-channel MOS transistor 11) becomes Vth+2xcex1. Thus, the input/output voltages required for the transistors to operate in the saturation region are lowered by an amount of the threshold voltage Vth, as compared with the cascode current mirror circuit of FIG. 1.
However, the aforementioned compound current mirror circuit requires two current sources 3, 3xe2x80x2 with high precision at the input side, causing problems of complication of circuit structure and increase of the electric current consumption.
The present invention has been carried out in view of the aforementioned circumstances, and it is therefore an object of the present invention to provide a current mirror circuit capable of precisely operating even at low input/output voltages.
To this end, as shown in FIG. 6, a low voltage current mirror circuit according to the present invention including multiple (two in the illustrated example) circuit elements 1A, 1B, each forming a current mirror, and concatenating the circuit elements 1A and 1B to constitute a cascode current mirror circuit, comprises voltage dropping means 2 for mutually connecting inter-control-electrode nodes of each of the circuit elements 1A, 1B to cause the predetermined voltage drop xcex2 between the inter-control-electrode nodes.
According to such a circuit structure, by providing the voltage dropping means 2, the control-electrode electric potential of the current mirror of the 1circuit element 1A becomes (Vth+xcex1)+xcex2, to thereby lower an input voltage and an output voltage by (Vth+xcex1)xe2x88x92xcex2 as compared with the control-electrode electric potential 2(Vth+xcex1) in the conventional circuit structure.
The circuit elements 1A, 1B, as shown in FIG. 6, may be constructed such that: the circuit element 1A includes an input transistor TR1 and an output transistor TR2, and the circuit element 1B includes an input transistor TR3 and an output transistor TR4, each of the input transistors TR1, TR3 and output transistors TR2, TR4 provided with a first terminal, a second terminal, and a third terminal connected to a control-electrode, and a current mirror is formed by mutually connecting between the third terminals of the input transistor TR1 and the output transistor TR2, and another current mirror is formed by mutually connecting between the third terminals of the input transistor TR3 and the output transistor TR4; in the adjacent circuit elements 1A, 1B, the first terminal of the input transistor TR3 is mutually connected to the second terminal of the input transistor TR1, and the first terminal of the output transistor TR4 is mutually connected to the second terminal of the output transistor TR2; in the circuit element 1A located at one end of the concatenation, the first terminal and the third terminal of the input transistor TR1 are connected to each other, the first terminal of the input transistor TR1 is supplied with an input current lin, and the first terminal of the output transistor TR2 is connected to an output terminal 4; and in the circuit element 1B located at the other end of the concatenation, each of the second terminal of the input transistor TR3 and the second terminal of the output transistor TR4 is applied with a reference voltage Vref.
Further, it is preferable that the voltage dropping means 2 causes the voltage drop xcex2 corresponding to a voltage a obtained by subtracting a threshold voltage Vth of the input transistor TR1 from a voltage between the second terminal and the third terminal of the input transistor TR1.
In this way, by setting the predetermined voltage drop of the voltage dropping means 2 to be xcex2=xcex1, the electric potential between the third terminals of the input and output transistors TR1, TR2 of the circuit element 1A becomes Vth+2xcex1, so that each of the output transistors TR2, TR4 of the circuit elements 1A, 1B operates in the saturation region when the electric potential at the output terminal 4 is 2xcex1 or higher, thereby enabling to obtain a large output resistance.
Further, as shown in FIG. 7, a specific constitution of the voltage dropping means 2 may include a first voltage dropping section 2A for mutually connecting the inter-control-electrode nodes of each of the circuit elements 1A, 1B, and a second voltage dropping section 2B for sending an electric current passed through the first voltage dropping section 2A to an input side current path. Alternatively, as shown in FIG. 8, the second voltage dropping means may be a second voltage dropping section 2Bxe2x80x2 for sending the electric current passed through the first voltage dropping section 2A to an output side current path.
According to such a construction, since xcex3+xcex7=Vth+xcex1 assuming that the voltage drop by the first voltage dropping section 2A is xcex3 and the voltage drop by the second voltage dropping section 2B is xcex7, the electric potential between the third terminals of the input and output transistors TR1, TR2 of the circuit element 1A becomes (Vth+xcex1)+xcex3=2(Vth+xcex1)xe2x88x92xcex7, thereby lowering the input voltage and output voltage by xcex7. Particularly, xcex3=xcex1 When xcex7=Vth, so that the electric potential between the third terminals of the input and output transistors TR1, TR2 of the circuit element 1A becomes Vth+2xcex1. Thus, each of the output transistors TR2, TR4 operates in the saturation region when the electric potential at the output terminal 4 is 2xcex1 or higher, thereby enabling to obtain a large output resistance.
The above specific constitution has been shown for a case of the two stages of circuit elements. However, such a constitution can be similarly applied to a case for concatenating circuit elements 1A, 1B, 1C in a three-staged manner as shown in FIG. 9, by providing first voltage dropping sections 2A1, 2A2 and second voltage dropping sections 2B1, 2B2. Such a constitution can be further extended to four or more stages of circuit elements.
Further, as shown in FIG. 10, another specific constitution of the voltage dropping means 2 may include a first voltage dropping section 2A for mutually connecting inter-control-electrode nodes of each of the circuit elements 1A, 1B, and a third voltage dropping section 2C for connecting between the first voltage dropping section 2A and an end terminal applied with the reference voltage Vth to cause the predetermined voltage drop Vth+xcex1, to thereby send the electric current passed through the first voltage dropping section 2A to the end terminal.
According to such a constitution, the electric potential between the third terminals of the input and output transistors TR3, TR4 of the circuit element 1B becomes Vth+xcex1 and the electric potential between the third terminals of the input and output transistors TR1, TR2 of the circuit element 1A becomes (Vth+xcex1)+xcex3, thereby enabling to lower the input voltage and output voltage, similarly to the above situation.